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Senior Design Verification Engineer

Austin, TX, US • Posted 22 hours ago • Updated 22 hours ago

Full Time

On-site

Depends on Experience

Fitment

Dice Job Match Score™

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Job Details

Skills

Summary

Job description:-

Title: Senior Design Verification Engineer
Location: Sunnyvale CA / Austin TX
Duration: ... FTE

Additional Job Details:

Key Responsibilities:
Strong understanding of SV and UVM and good debugging skills.
Understanding of AMBA protocols.
Understand design specs and develop test plans based on functional and architectural requirements
Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing
Develop directed and random testcases, perform coverage analysis, and close functional/code coverage
Debug simulation failures and work closely with RTL designers to resolve issues
Execute regression runs, analyze results, and contribute to continuous improvements
Integrate and run power-aware simulations, low power checks, and work with UPF/CPF as needed
Collaborate with DFT/PD/RTL teams and post-silicon validation to ensure design quality across domains
Document test environments, testplans, and results for internal and external reviews

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10117909
Position Id: 26-09328
Posted 22 hours ago

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