Hi,
Hope you are doing well.
I have an urgent opening of Principal RTL Lead High-Speed Ethernet ASIC (400G/800G) at San Jose, CA
Position Type: Contract
Location: San Jose, CA, United States
Virtual
Onsite: San Jose, CA (Local)
Principal RTL Lead High-Speed Ethernet ASIC (400G/800G)
JD:
We are hiring a Principal RTL Lead to drive the design and development of next-generation Ethernet subsystems for custom ASIC silicon, supporting 400G/800G+ data center infrastructure.
This is a highly technical, hands-on role focused on solving complex challenges in high-speed digital design, multi-lane data processing, and Ethernet protocol implementation.
Key Responsibilities
- Define micro-architecture for high-bandwidth datapaths and control logic
- Lead System Verilog RTL design for Ethernet subsystems
- Implement IEEE 802.3 standards, including:
- RS-FEC (Reed-Solomon)
- Multi-Lane Distribution (MLD)
- Auto-Negotiation / Link Training (AN/LT)
- Solve complex design challenges:
- Wide data paths (1024-bit+)
- Timing closure at high frequencies
- Clock domain crossing (CDC) across asynchronous boundaries
- Lead integration of SerDes IP and ensure PHY MAC interoperability
- Drive best practices across:
- Lint / CDC / RDC
- Power optimization (UPF)
- Design quality for first-pass silicon success
Required Experience
- 10+ years in ASIC RTL design (System Verilog)
- Proven track record of multiple successful tape-outs (7nm / 5nm / 3nm preferred)
- Deep expertise in high-speed Ethernet (100G / 400G / 800G)
- Strong understanding of MAC / PCS / FEC layers
- Experience across full ASIC front-end flow (architecture RTL verification bring-up)
- Ability to lead subsystem design and mentor engineers
Nice to Have
- IEEE 1588 (PTP) hardware timestamping
- PCIe Gen5/6 or CXL
- Python / Perl scripting for design automation
- Experience working closely with physical design teams (timing / congestion)
Regards,
Nitin Gupta
Team Lead-Recruitment
ShiftCode Analytics Inc.,
5118 Sylvester loop Tampa,
Florida 33610
Direct:
Email:
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