Physical Design Engineer@Bay Area,CA

Physical Design EngineerBay Area, CABelow is the Job Description:Good understanding of Cadence tools (Innovous, Quantus, Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floorplanning, CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.Experience with CDC, stati

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

Physical Design Engineer Bay Area,CA (onsite) Longterm Contract Good understanding of Cadence tools(Innovous,Quantus,Voltus).Deep knowledge about industry standards in Physical Design, Physical aware synthesis,Floorplanning,CTS and place and route.Experience in developing and implementing Power-grid and high speed clock constraints and specifications.Experience with CDC,static timing analysis methodologies and relevant tools.Understanding and experience of mixed signal environments is a must.Can

Position:Physical Design Engineer II (IC) Job Description:Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively identify and