The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and band gap references.
As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes.
BS and 10+ years of relevant industry experience.\nFinFet experience.
Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.\nKnowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.\nSolid understanding of RC delay, electromigration, and coupling.\nUnderstanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD, WPE.\nHigh level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.\nKnowledge of CADENCE layout tools.\nExcellent communication skills.\nScripting skills in PERL or SKILL.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: 90733111
- Position Id: e0818ad003ccd2d4687ae9a0265be35e
- Posted 18 hours ago
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