CPU Power Management Microarchitect/RTL Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! \\n\\nApple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions.

As a CPU RTL Architect, you will own or participate in the following: \n\n Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification\n RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals\n Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification\n Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance\n Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power

Minimum BS and 10+ years of relevant industry experience\nExperience with microprocessor architecture\nExperience with logic design principles with timing and power implications\nExperience in Verilog or VHDL\nExperience with simulators and waveform debugging process

Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies\nUnderstanding of low power microarchitecture techniques \nUnderstanding of high-performance techniques and trade-offs in a CPU microarchitecture \nExperience in C or C++ programming \nExperience using an interpretive language such as Perl or Python