Job Title: FPGA Verification Engineer
Location: Hybrid (4 days at Cisco SJ office and 1 day remote)
Duration: 12 months
Rounds of interview: There will be a total of 2 rounds: 1 screening, the second will be in-depth with 2 engineers"
Job Description
• Own verification of entire FPGA design used in high-end router products.
• Understand design specifications and interact with design engineers to identify verification scenarios.
• Create test plans, constrained-random verification environments, testcases, regressions, and coverage reports.
• Identify and write all types of coverage measures for stimulus and corner-cases.
Candidates must meet the minimum requirements outlined.
• Strong academic background in Electrical Engineering (Bachelor''s required, Master''s preferred)
• 7-10 years of pure verification experience in ASIC/FPGAs
• Experience with PCIe, Ethernet, slow speed interfaces like I2C, SPI, MDIO, etc, and developing object-oriented testbench infrastructure, BFMs, and testcases in UVM.
• Ability to independently develop test plans, test sequences, generate stimuli, and collaborate with RTL designers to debug failures.
• Experience with scripting languages like Perl, Python.
• Proficiency with industry-standard tools, revision control systems, and regression systems.