CPU Processor Power Management Verification Engineer

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!\\n\\nIn this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification.

As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows: \n\n Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic\n Develop and execute test plans and schedules for the power management and clock control logic\n Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments\n Root cause failures and propose potential solution to the design team\n Work with silicon bringup team on developing tests that work in the emulation and FPGA environments. Aid silicon debug in related part of the design\n Develop coverage monitors and analyze coverage to ensure all the test cases in the test plans are covered\n Develop checkers or Verilog/System Verilog-base transactor to verify the design\n Write assertions and apply formal verification to the design

Minimum BS\nAcademic experience in computer architecture\nAcademic experience in digital design using Verilog

Master's degree preferred\nKnowledge of digital logic, micro-processor architecture and power management architecture\nProficiency in programming and scripting in Python, or Perl, or TCL\nExperience or academic knowledge in design verification methodology. Understanding of verification testplans, Verilog/System-Verilog testbenches, transactors and checkers\nKnowledge of system Verilog assertions or other advance verification techniques such as formal verification is a plus\nShould be an extraordinary teammate with excellent communication skills with the ability to articulate complex design issues during verification efforts\nBe able to follow detailed work schedules and work independently on the verification efforts for a block/area of the design