3D IC Design / EDA Research Engineer

San Jose, CA, US • Posted 6 hours ago • Updated 6 hours ago
Contract W2
12 Months
No Travel Required
On-site
$70 - $75/hr
Fitment

Dice Job Match Score™

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Job Details

Skills

  • C++
  • Circuit Design
  • EDA
  • Electronic Design Automation
  • Python
  • VLSI
  • 3DIC
  • 3D-IC
  • Research
  • publication
  • R&D

Summary

Seeking an experienced 3D IC Design / EDA Research Engineer to join our growing team. The ideal candidate will focus on researching and developing advanced Electronic Design Automation (EDA) algorithms, innovative 3D IC design methodologies, and next-generation semiconductor integration technologies. This role is onsite in San Jose, CA and its  involves exploring fine-grained 3D integration, optimizing RC delays, developing advanced physical design solutions, and contributing to cutting-edge research initiatives through technical publications and patents.

Job Responsibilities:

  • Investigate advanced 3D IC design methodologies and EDA algorithms guided by the Tau (τ) Scaling Law to reduce RC delay and optimize performance from the device level to the system level.
  • Explore fine-grained 3D integration methodologies, including logic folding across hybrid-bonded tiers, 3D partitioning, placement and routing, clock and power optimization, and thermal management.
  • Support emerging technology and research initiatives by developing and implementing leading-edge proofs of concept while following established engineering best practices.
  • Lead and contribute to technical research papers and patent development as key research deliverables.
  • Maintain broad technical knowledge across multiple research domains while developing deep expertise in at least one specialized technical area.
  • Track emerging advancements in EDA, 3D integration, Design Technology Co-Optimization (DTCO), System Technology Co-Optimization (STCO), and AI/ML applications for EDA, while investigating critical research challenges.
  • Collaborate with internal and academic researchers across EDA, circuit design, semiconductor process technology, advanced packaging, and computer architecture.
  • Work with management to communicate complex technical concepts and research findings in internal and external technical forums.
  • Conduct experiments, validate research ideas, and effectively communicate technical results through presentations, publications, and written documentation.

Required Skills & Experience:

  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or Physics, with a strong background in EDA or VLSI design.
  • Established publication record in recognized EDA/VLSI conferences and journals, such as DAC, ICCAD, DATE, ISPD, or IEEE TCAD.
  • Strong background in research, algorithm development, and software engineering using C++ and Python.
  • Solid understanding of semiconductor physical design concepts, including placement, routing, Clock Tree Synthesis (CTS), Static Timing Analysis (STA), and parasitic extraction.
  • Good understanding of 3D IC integration technologies, including hybrid bonding, Through-Silicon Vias (TSVs), and chiplet-based architectures.
  • Hands-on experience with commercial or open-source Electronic Design Automation (EDA) tools.
  • Ability to investigate complex technical challenges, develop innovative solutions, and communicate research findings effectively.
  • Strong written and verbal communication skills, with the ability to present and explain complex research concepts.

Preferred Skills & Experience:

  • Hands-on experience with 3D IC design and implementation workflows.
  • Experience applying Machine Learning (ML) or Artificial Intelligence (AI) techniques to EDA algorithms and physical design optimization.
  • Research experience in Design Technology Co-Optimization (DTCO), System Technology Co-Optimization (STCO), and advanced semiconductor integration.
  • Experience contributing to technical publications, patents, and collaborative research initiatives.
  • Familiarity with emerging semiconductor technologies, advanced packaging methodologies, and next-generation chip architectures.

Education Required:

  • PhD in Electrical Engineering, Computer Engineering, Computer Science, or Physics, with specialization or research experience in EDA, VLSI design, or a related semiconductor technology domain.

 


AgreeYa is a global systems integrator delivering competitive advantage for its customers through software, solutions, and services. Established in 1999, AgreeYa is headquartered in Folsom, California, with a global footprint and a team of more than 2,200 staff across offices. AgreeYa works with 500+ organizations ranging from Fortune 100 firms to small and large businesses across industries such as Telecom, Banking, Financial Services & Insurance, Healthcare, Utility & Energy, Technology, Public Sector, Pharma & Biotech, and others. Please visit us at for more information.

AgreeYa is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, gender identity, sexual orientation, national origin, disability, veteran status, or other protected characteristics. Visit our website to learn about our Career & Culture.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: swapps
  • Position Id: 9140765
  • Posted 6 hours ago
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