Physical Design Engineer

Job Title: Physical Design Engineer (5 10+ Years Experience)

Location: Bay Area, CA / Texas - (Onsite)

Experience: 5 10+ Years

Domain: VLSI / Semiconductor / ASIC Physical Design

Job Summary

We are seeking an experienced Physical Design Engineer with 5 10+ years of hands-on experience in ASIC physicaldesign. The candidate will be responsible for end-to-end block/full-chip physical design activities from RTL2GDSII/Netlist2GDSII, ensuring high- quality, STA, SI, EMIR and PV (DRC/LVS/ERC/ANT)-clean layouts.

Key Responsibilities

• Drive full-chip SoC/Block level physical design from RTL2GDSII/Netlist2GDSII
• Perform top-level/sub-system/Block synthesis, floor planning, partitioning, and hierarchical integration
• Develop and implement full-chip/Block level power planning and power grid strategies
• Manage block integration, timing budgeting, and interface closure
• Execute and optimize placement, CTS, routing, and post-route flows at full-chip level
• Lead full-chiptiming closure across MMMC scenarios
• Handle top-level congestion, SI, noise, IR drop, and EM closure
• Perform and drive physical verification closure (DRC/LVS/ERC/ANTENNA)
• Manage ECO flows including full-chip and block-level ECOs
• Collaborate closely with RTL, synthesis, STA, DFT, packaging, and verification teams
• Support tapeout planning, signoff checks, and final delivery milestones
• Build and enhance automation scripts and PD flows

Required Technical Skills

• Strong experience in full-chip SoC implementation
• Deep expertise in:
• Top-level floorplanning and partitioning
• Chip-level power planning and multi-voltage domains
• Hierarchical and flat implementation flows
• Timing budgeting and interface timing closure
• CTS and clock architecture at SoC level
• Congestion and routing optimization
• Strong knowledge of:
• MMMC timing setup and closure
• OCV/AOCV/POCV, SI and Crosstalk analysis
• Multi-voltage and low-power flows (UPF/CPF)
• IR/EM and thermal considerations

• Hands-on experience with tools such as:
• Cadence Innovus / Synopsys ICC2
• PrimeTime / Tempus
• Voltus / RedHawk
• Calibre / Pegasus

Preferred ualifications

• Experience in advanced nodes ( 16nm / 7nm / 5nm preferred)
• Exposure to large SoC designs with multiple clock and power domains
• Experience handling high-speed interfaces and hard macros
• Knowledge of packaging interactions and bump/IO planning
• Strong Tcl scripting skills; Python/Shell scripting is a plus
• Experience mentoring engineers and leading PD closure tasks

Soft Skills

• Strong debugging and problem-solving skills
• Ability to work independently and drive closure
• Good communication and cross-team collaboration skills
• Experience mentoring junior engineers (preferred for senior candidates)

Education

• B.E./B.Tech/M.E./M.Tech in Electronics / VLSI / Electrical Engineering or related field