FE Engineering

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Description

APPLE INC has the following available in Austin, Texas. Responsible for Logic Synthesis for Apple GFX Partitions. Responsible for LEQ/ATPG/DFT/Lint clean designs. Run various experiments to help in achieving the best design QoR metrics (Power, Performance, Area). Work closely with the RTL and PD (physical design) teams. Responsible for synthesis, analysis, and optimization of the delivered IP. Use and develop advanced techniques spanning RTL/Synthesis/Place and Route to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Implement logically coded (RTL) design with technology specific silicon netlist with product area, power and performance goals with required design validation checks performed. Run various synthesis trials in industry tools and analyze the reports to improve power, performance and area of the design owned as part of Apple Graphics team. Collaborate with IP team and Physical design team to address design issues and generate ideas to enhance the design. Ensure the synthesized netlist is power clean, logically equivalent and Lint clean and has the best quality of result. Ensure that the DFT (Design for Test) chains are successfully inserted in all the designs with good test coverage. Debug issues and suggesting solutions collaborating with vendors and CAD (Computer Aided Design) support teams. Explore possibilities to automate the existing flows and explore the possibilities of creating utilities which can assist in improving design quality. Perform ECO's to address changes on the netlist post release. Perform signoff checks at the end of design cycle to ensure that the design meets acceptable criteria and quality. 40 hours/week.

Minimum Qualifications

Master's degree or foreign equivalent in Electrical Engineering or related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include:

Utilizing experience in performing physical synthesis to optimize digital circuit designs for power, performance, and area (PPA) trade-offs.

Utilizing experience in analyzing and debugging digital logic described in Hardware Description Languages (HDLs), such as Verilog or System Verilog, at the Register Transfer Level (RTL).

Utilizing experience in performing formal logic equivalence verification between Register Transfer Level (RTL) and gate-level netlists.

Utilizing experience in performing static timing analysis (STA) to identify and debug timing violations on critical paths within a digital circuit design.

Utilizing experience in developing scripts using languages such as Python, Perl, or Tcl to automate design flows, data extraction, and reporting tasks.

Implementing and verifying functional and timing Engineering Change Orders (ECOs) at the gate-level netlist.

Analyzing designs that incorporate multiple power domains defined by a Unified Power Format (UPF) specification.

Preferred Qualifications

N/A