Verification Engineer

As a Verification Engineer at IMC, you will be part of the R&D team. You'll have the opportunity to work on novel solutions to accelerate trading decisions to the technological limit. In addition, you'll work on forward looking solutions that anticipate future requirements. Your Core Responsibilities: Work in a small and globally distributed team that takes responsibility for the complete solutionCollaborate closely with RTL and SW team to validate complex systemsAutomate verification flow for

Team Red Dog is hiring a Senior Hardware Verification Engineer - SystemVerilog/UVM for our client, a Fortune 50 technology leader and next-generation cloud platform company. This fully remote, senior-level role will drive pre-silicon hardware design verification for accelerated networking technologies, developing and executing comprehensive verification strategies using SystemVerilog, UVM, and coverage-driven methodologies. You will work within sophisticated IP and SoC verification environments

Position: DV IP Design Verification Engineer Location: Remote Employment Type: Contract Job SummaryWe are looking for an experienced Design Verification Engineer with strong expertise in IP/Block-level verification to support verification of complex digital IPs. The ideal candidate will have hands-on experience developing SystemVerilog/UVM-based verification environments, creating verification plans and testcases, debugging RTL and testbench issues, and driving functional/code coverage to closur

Position: DV SOC / SoC Design Verification Engineer Location: Remote Job Type: Contract Job SummaryWe are looking for an experienced SoC Design Verification Engineer to support SoC-level verification, integration, and signoff activities for complex ASIC/SoC designs. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, SoC verification, RAL, low-power verification using UPF, Gate-Level Simulation (GLS), and coverage closure. This role will involve integrating IPs/UVCs