DFT Engineer

Title: Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills & Experience 3+ years of experience working as a DFT Engineer.Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improv

DFT (Design for Test) Engineer. Location: Santa Clara, CA Key Skills & Experience Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite. Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing. Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement. Experience with MBIST (Memory Built-In Self-Test), including memory test ar

Position: DFT engineer Location: Santa Clara, CA Duration: Long Term ATPG experience is not mandatory for candidates to submit going forward. More DFx and other DFT skills are required. Job details:- Familiarity with the Siemens suite of DFT tools DFT insertion for SCAN (with SSN) and MBIST MBIST Repair Implementation and Verification Generating collaterals for Test Timing and Place and Route Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec Verification of DF

Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC levelVerify test patterns using gate-level simulations.Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems.Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of indust