Title: ASIC/SoC RTL Design Engineer Location: Palo Alto, CA (Or potentially Burlington, MA) Length of Contract: 6 months+ (Temp-to-Perm) Ideal Start: 6/1/2026 Responsibilities : Own end-to-end design of complex SoC subsystems, driving architecture, RTL implementation, and tapeout. Focus on high-performance Datapath, PPA optimization, and cross-functional integration across silicon, firmware, and system teams. Must haves: 8 12+ years in ASIC/SoC digital design with hands-on RTL ownershipStrong Sy

Xona is the navigational intelligence company bringing real-time, centimeter-level certainty to any device, anywhere on Earth. With Pulsar - the world's most advanced PNT satellite infrastructure in Low Earth Orbit - Xona will offer a future-proof, backwards-compatible global positioning system optimized for absolute precision, superior power, and robust protection. We're seeking an FPGA Engineer to design and implement high-performance, signal-processing solutions for next-generation LEO PNT

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

We are seeking a Senior Digital/AMS Design Engineer to drive the integration of complex digital logic into our industry-leading Automotive SerDes transceivers. In this role, you will be responsible for the RTL design of the "Digital-Analog Wrapper," ensuring seamless control and data flow between high-speed analog front-ends and the DSP/Link-layer logic. You will own the path from RTL through timing closure and support the validation of that logic in the lab. Key Responsibilities RTL Design & I