Principal RTL Design Engineer

 

 

• Lead the design and implementation of complex RTL blocks, modules, and subsystems using Verilog/SystemVerilog for NPU architectures.
• Collaborate with system and microarchitecture architects to define and refine specifications, translating requirements into robust RTL solutions.
• Drive architectural and RTL decisions to optimize performance, power efficiency, and area (PPA) for AI workloads.
• Design and optimize compute engines, data paths, and memory hierarchies for high bandwidth, latency-sensitive neural network processing.

• Own timing analysis and timing closure strategies for complex designs, identifying and resolving critical paths.
• Apply advanced low-power techniques, including clock gating and power-aware design methodologies, to meet aggressive power targets.
• Lead area optimization efforts while preserving functional correctness and performance goals.
• Ensure testability by guiding and implementing test design (DFT) strategies to support silicon validation and manufacturing readiness.

 

Integration, Validation & Technical Leadership (10%)
• Provide technical leadership during RTL integration, working closely with verification teams on simulation, emulation, and FPGA prototyping.
• Partner with software, hardware, and system teams to ensure seamless integration of the NPU into the broader vehicle compute platform.
• Review designs, mentor engineers, and set best practices for RTL quality, correctness, and maintainability.
• Author and review technical documentation, including design specifications, architecture reviews, and implementation guidelines.

 

Technology Direction & Cross Functional Influence (10%) 
• Influence RTL and hardware development methodologies across programs, contributing to consistency and scalability of design practices.
• Evaluate emerging tools, technologies, and design approaches relevant to AI accelerators and automotive hardware platforms.
• Communicate complex technical concepts clearly to both technical and nontechnical stakeholders, supporting informed decision making.

 

Mandatory Skills Description:
• Expert communicator across global, cross-cultural, and cross-functional teams.
• Strong analytical, system-level, and architectural thinking.
• Proven ability to lead technical initiatives without direct authority.
• High bar for design correctness, validation, and quality.
• Collaborative mindset across hardware, software, and verification organizations.
• Extensive experience in RTL design using Verilog/SystemVerilog for complex digital systems, preferably NPUs or AI accelerators.
• Proficiency with EDA tools for synthesis, simulation, and timing analysis (Synopsys, Cadence, Mentor).
• Strong understanding of computer architecture, microarchitecture, and hardware/software co design.
• Experience with FPGA prototyping, emulation platforms (e.g., VCS, Palladium), and HW/SW co-verification.
• Scripting experience (Python, Perl) for automation and productivity.
• Deep knowledge of low-power design and power optimization techniques.
• Demonstrated track record of delivering complex RTL designs from concept through silicon production.