Senior Physical Designer / STA Engineer

Job Title: Senior Physical Designer / STA Engineer ( W2 ONLY )

Location: BAY AREA / AUSTIN, CA

Experience: 5–10+ years

Job Summary:

We are seeking a highly skilled Senior Physical Designer / STA Engineer to join our ASIC/SoC design team. The ideal candidate will have deep expertise in digital physical design, timing closure, and static timing analysis, and will play a critical role in delivering high-performance, area-optimized, and power-efficient designs.

Key Responsibilities:

Physical Design:

• Lead full-chip physical design activities including floorplanning, placement, clock tree synthesis (CTS), routing, and ECOs.
• Collaborate with RTL and synthesis teams to optimize timing, area, and power trade-offs.
• Perform design for manufacturability (DFM) and design rule checks (DRC/LVS) in coordination with backend tools.
• Mentor junior engineers and contribute to the improvement of physical design flows and methodologies.

Static Timing Analysis (STA):

• Perform timing analysis and closure using tools like Synopsys PrimeTime, Cadence Tempus, or equivalent.
• Develop timing constraints and verify setup, hold, clock skew, and timing exceptions.
• Identify and resolve timing bottlenecks and provide timing sign-off for tape-outs.
• Collaborate with synthesis, verification, and physical design teams to achieve timing closure under process, voltage, and temperature (PVT) variations.

Cross-functional Collaboration:

• Work closely with architects, RTL designers, and verification teams to ensure design meets performance, power, and area (PPA) targets.
• Support ECOs during late-stage design cycles and post-silicon timing analysis.
• Contribute to process technology migration and tool flow enhancements.

Required Skills and Experience:

• Strong expertise in digital ASIC/SoC physical design: floorplanning, placement, CTS, routing, ECOs.
• Hands-on STA experience: setup, hold, timing exceptions, multi-mode multi-corner (MMMC) analysis.
• Proficient with EDA tools: Synopsys (IC Compiler II, PrimeTime, Fusion Compiler), Cadence (Innovus, Tempus), Mentor (Calibre) or equivalent.
• Knowledge of timing constraints: SDC creation, clock definitions, false paths, multicycle paths.
• Understanding of power optimization techniques (clock gating, multi-Vt, dynamic voltage scaling).
• Familiarity with DFT, signoff flows, and process technology nodes (28nm, 16nm, 7nm, 5nm, or below).
• Strong analytical, problem-solving, and debugging skills.
• Excellent communication and team collaboration skills.