Field-Programmable Gate Arrays Engineer

Position: FPGA Verification Contractor

Location: San Jose, CA (Onsite)

Duration: Long-term contract role

Job Description & Responsibilities

• Own verification of the entire FPGA design used in high-end router products
• Understand design specifications and collaborate with design engineers to identify verification scenarios
• Create test plans, constrained-random verification environments, test cases, regressions, and coverage reports
• Identify and write all types of coverage measures for stimulus and corner cases

Qualifications

• Strong academic background in Electrical Engineering
• Bachelor’s required, Master’s preferred
• 7–10 years of pure ASIC/FPGA verification experience
• Proficient in SystemVerilog with clear OOP concepts
• Experience developing object-oriented testbench infrastructure, BFMs, and testcases in UVM
• Experience with PCIe, Ethernet, and slow-speed interfaces such as I2C, SPI, MDIO
• Strong understanding of IP integration verification, strategies, and corner cases
• Ability to independently:
• Develop test plans
• Create test sequences
• Generate stimuli
• Collaborate with RTL designers to debug failures
• Experience with scripting languages such as Perl and Python (plus)
• Proficiency with industry-standard tools, revision control systems, and regression systems

Expectations

• Professional attitude; strong team player with ability to work independently
• Ability to prioritize tasks and manage multiple projects in parallel
• Adaptable and flexible to switch tasks based on priorities
• Strong communication skills
• Role involves significant interaction with the team
• Expected to work onsite most of the time