Senior Design Verification Engineer

Role: Senior Design Verification Engineer

Location -Sunnyvale, CA-Onsite
No of Positions - 2
Exp needed - 8 to 10 yrs
Duration - Longterm

Here is the JD:

Responsibilities
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause, and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality

Minimum Qualifications
B.S or M.S degree in Electrical Engineering, Computer Engineering or Computer Science
Hands-on experience in Verilog, SystemVerilog, C/C++ based verification, and UVM methodology
Experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, Perl, Shell) used to build tools and flows for verification environments.
Experience in architecting and implementing Design Verification infrastructure and executing the complete verification cycle

Preferred Qualifications
Experience in the development of UVM based verification environments from scratch
Experience with Design verification of Data-center applications like Video, AI/ML, and Networking designs
Experience with revision control systems like Mercurial(Hg), Git or SVN
Experience with verification of ARM/RISC-V based sub-systems or SoCs