RTL Design Engineer / Design Verification Engineer

R-069895 RTL Design Engineer – Wireless SoC (Remote – PST)

Location: Remote (must be aligned with PST time zone / willing to work PST hours)  

We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silicon.

🔹 Required Skills

5+ years of hands-on RTL design experience (SystemVerilog / Verilog)

Strong understanding of micro-architecture and RTL implementation from specs

Experience in DSP hardware implementation (filtering, FFT, etc.)

Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verification

Experience with synthesis, linting, simulation, and STA tools

Understanding of DFT concepts (scan, BIST)

Strong debugging and problem-solving skills

Good communication and ability to work in cross-functional teams

🔹 Key Responsibilities

Design, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Verilog

Translate architectural and algorithmic specifications into synthesizable RTL

Implement DSP blocks such as filtering, FFT/IFFT, beamforming, etc.

Develop RTL for SoC components including interfaces, clock/reset, power management, and debug logic

Work with internal and external IP integration into chip-level designs

Collaborate with AMS teams on digital-analog interfaces, calibration logic, and control systems

Drive PPA (power, performance, area) optimization and support timing closure with backend teams

Participate in design reviews, integration, synthesis, and timing closure activities

Support silicon bring-up and lab validation of digital subsystems

JR069896 - Design Verification Engineer

Role – Design Verification Engineer

Location – - Remote (must be aligned with PST time zone)

Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.

3+ years of experience in ASIC/SoC verification.

Solid understanding of SystemVerilog, digital logic, and hardware verification flows.

Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.

Experience with test planning, testbench development, constrained-random testing, and coverage analysis.

Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.

Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.

Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.

Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.

Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.

Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.

Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.

Participate in design reviews and microarchitecture discussions.