Job Summary

We are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test insertion, and validation for complex SoCs. You will work closely with design, verification, and product engineering teams to ensure high-quality, testable silicon.

Key Responsibilities

• Define and implement DFT architecture for complex SoCs
• Scan insertion, ATPG, and scan pattern validation
• MBIST insertion, debugging, and validation
• Boundary Scan (JTAG), IJTAG, and DFT-related protocols
• Work with RTL designers to ensure DFT-friendly design
• Run and debug DFT-related lint checks and simulations
• Support silicon bring-up, test, and failure analysis
• Collaborate with product engineering and ATE teams
• Review DFT coverage, diagnostics, and test quality metrics
• Develop and maintain DFT documentation and test plans

Required Skills & Experience

• 6+ years of hands-on experience in DFT for ASIC/SoC designs
• Strong knowledge of:
  • Scan Insertion and ATPG (Synopsys Tetra/Siemens Tessent or Cadence tools)
  • MBIST (Memory BIST) implementation and debug
  • JTAG/Boundary Scan and IJTAG concepts
  • RTL-to-GDS DFT flow
• Experience with low power DFT (Clock gating, isolation, retention strategies)
• Familiarity with STA and timing impact of DFT
• Good understanding of test coverage, diagnostics, and yield analysis
• Experience working with multi-clock, multi-voltage designs is a plus

Preferred Qualifications

• Experience with advanced nodes (7nm, 5nm, or below)
• Familiarity with ATE and production test flows
• Experience in post-silicon debug and validation
• Strong scripting skills (Python, Perl, or Tcl)
• Excellent communication and collaboration skills

Education

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering, VLSI, or related field.