We have an immediate opportunity for a Post Silicon Validation Engineer to support validation activities for advanced ML Coprocessors, Display SoCs, Mixed Signal SoCs, and complex IP blocks. The ideal candidate will be responsible for defining silicon validation strategies, creating comprehensive test plans, and collaborating closely with RTL, architecture, firmware, and software teams to ensure robust validation coverage across the product lifecycle. To be successful in this position, one needs to be highly experienced in post-silicon bring-up, debug methodologies, validation automation, and system-level characterization in complex SoC environments.
The consultant will develop and enhance silicon validation infrastructure using C/C++ and Python across emulation platforms such as Zebu, FPGA platforms including HAPS, and first silicon environments. Responsibilities include enabling workloads, validating ML accelerator software stacks, executing bring-up and debug activities, and performing detailed performance and power characterization using real-world ML workloads. The role also involves creating automated data collection and reporting flows, transforming large datasets into executive-level summaries, tracking validation coverage, documenting defects, driving cross-functional debug efforts, and verifying silicon fixes.
In addition, the engineer will actively participate in design and architecture reviews, provide recommendations to improve validation quality and coverage, and collaborate with factory test and production teams to align silicon validation with production characterization strategies. Strong communication skills and the ability to work effectively across hardware, firmware, software, and manufacturing teams are essential for success in this role.
Interested candidates are encouraged to connect with our recruiter.
Narasimha
PRIMUS Global Services
Phone: Desk Ext. 267
Email:
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