Post Silicon Validation Engineer

Key Skills: Post Silicon Validation,Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl Conduct initial power-on, reset sequencing, clock bring-up, and strap configuration for complex networking ASICs or SoCsEValidate Ethernet (e.g., 100G/400G/800G) MAC/PHY and PCIe (Gen 4/5/6) interfaces for physical layer integrity.Develop, execute, and automate validation test plans and SDK-driven test environments using Python & C/C++.Root-cause complex silicon, link training, and firmware bu

Position: Post silicon Validation engineer Exp: 10+ years Location: Sanjose,CA Key Skills: Post Silicon Validation, Oscilloscope, Multimeters, Analyzers, PCIe, Ethernet, Python, Perl Conduct initial power-on, reset sequencing, clock bring-up, and strap configuration for complex networking ASICs or SoCs EValidate Ethernet (e.g., 100G/400G/800G) MAC/PHY and PCIe (Gen 4/5/6) interfaces for physical layer integrity. Develop, execute, and automate validation test plans and SDK-driven test environme

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t