IC Layout Engineer

*On-site interview in Austin, TX required*

Holders

16nm / FF / TSMC

Qualifications & Competencies:
Associates or higher degree in Electronic/IC layout CAD specialization or related program.
5+ years experience in IC layout design.
FinFET analog circuit layout experience is required, with preference in TSMC 1x technology node.
Strong understanding of layout fundamentals and best practices.
Solid understanding of semiconductor manufacturing process and DFM techniques.
Must be knowledgeable with CAD tools like Cadence Virtuoso XL, PVS/Calibre.
Proficient at debugging/fixing LVS/DRC errors.
Must be familiar with Cadence Design Environment (CDE) and Unix OS.
Must have strong communication skills and be a team player.
Unquestionable ethics treats people with respect; keeps commitments; inspires the trust of others; works with integrity.
Commitment to our core values of Leadership, Innovation, Communication, Persistence, Enthusiasm, and Respect.