Verification Engineer

Austin, TX, US • Posted 30+ days ago • Updated 20 minutes ago
Full Time
On-site
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Videoconferencing
  • Venture Capital
  • Synopsys
  • Cadence
  • SVA
  • Scripting
  • Tcl
  • Python
  • Perl
  • FOCUS
  • Formal Verification
  • SystemVerilog
  • UVM

Summary

Job Description

Description:
Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence)
Strong proficiency in System Verilog Assertions (SVA) and formal property specification
Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
Familiarity with scripting languages (TCL, Python, Perl) for flow automation
Extensive experience in design verification with a strong focus on formal verification
Expertise in System Verilog and UVM-based verification methodologies - Nice to have

Meet Your Recruiter

Ana Kirby
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10375359
  • Position Id: 81805b28fe96cc9311c06b09ecad3e05
  • Posted 30+ days ago
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