EDA/HPC Architect

Location: US remote (travel to Malaysia is required once per quarter - travel will be funded by the client)

Duration: 6+ Months

Key Responsibilities

l Infrastructure Design: Architect high-performance, scalable clusters tailored for RTL simulation, logic synthesis, and physical design workloads.

l Tool Optimization: Experience working with CAD teams to tune infrastructure for peak performance of industry-standard tools like Synopsys IC Compiler II/Fusion Compilerand Cadence Virtuoso/Innovus.

l Storage & Data Management: Familiar with low-latency, high-throughput storage requirements for Flash/NVMe systems capable of handling the high-I/O metadata requirements and multi-terabyte datasets.

Required Qualifications

l Experience: 7–10 years of professional experience in HPC / EDA systems architecture, with a focus on the semiconductor or electronics industry.

l Software Proficiency: Knowledge of the infrastructure interdependencies of Synopsys and/or Cadence design environments.

l Technical Stack:

l Experience with Linux administration and kernel tuning for EDA.

l Familiar with scripting languages (Python, Bash, or Perl) for automation.

l Familiar with high-performance networking (InfiniBand/High-speed Ethernet).