Hi,
I hope all is well. I am doing a search for a client who has an urgent requirement for a network administrator contract opportunity. The job description is listed below. If this is something you are interested in, please call me ASAP at . please mail me your updated resume in Word format, availability, contact details, and hourly rate as per the hiring policy of our client.
ASIC Verification Engineer
About the role:
PCIe Protocol IP Verification Expert: Consulting & Turnkey projects The client semiconductor BU is looking for seasoned professionals in the ASIC Verification domain.
Client is invested in AI/HPC [High-Performance Computing] customers who are emphasizing on shift left pre-silicon approaches.
IP integration and interoperability with multiple Vendor PHY is becoming important to be validated for SOC Integration & Bring Up.
Complex System Level Environment targeting latest protocol interfaces & switches for scale up and scale out data centers
Client is looking for PCIe protocol experts to integrate the 3rd Party IP’s [Synopsys, Cadence, Qualitas & other Vendors] with Rambus PCIe Gen6 controller/PHY & validate with complete regression suite.
Job Description
Application or Product Engineering background with minimum 5 to 10 years of experience is required in SOC/IP Verification.
Deep Knowledge of FW/SW/Driver with linkup/enumeration/device ID/interoperability of PCIe IP [Gen1 to Gen6/7] plus PHY in subsystem or SOC level .
Skills Requirements
- Digital design with system verilog RTL coding at IP/System Integration level.
- Experience with one of the simulators like Questa , VCS & Xelium.
- Ability to put together top-level wrapper with PCIe DUT at sub system level with PHY [Root Complex & End Point Device], clocks/reset & glue logic required.
- Ability to understand the complex scripted simulation regression environment with UVM & C/C++ testbenches, modify to enhance the test suit and do the functional verification.
- Knowledge of Python, C/Perl scripting is required. Expertise in debugging the complex PCIe bring up scenarios like LTSSM state machines for link up & enumeration steps.
- Understand the configurations of all Generations of PCIe combinations for debugging the failures.
Verification Engineer1PCIe,RTLN/AC2C,W2United States
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