Lead ASIC DFT Staff Engineer

Company: TechAGI Solutions
Location: Remote (Must align with PST working hours)
Job Type: Contract – C2C / W2
Rate: $110/hr C2C | $100/hr W2
Experience: 10+ Years
Work Authorization: Any valid U.S. work authorization

Job Description

We are looking for an experienced Lead ASIC DFT Staff Engineer with 10+ years of hands-on experience in ASIC Design-for-Test (DFT), SCAN, ATPG, MBIST, timing simulations, and post-silicon debugging.

The ideal candidate should have strong experience in DFT architecture, implementation, verification, and silicon validation for complex ASIC and SoC designs.

Key Responsibilities

• Lead DFT architecture, implementation, verification, and sign-off for ASIC/SoC designs.

• Perform scan insertion, scan chain stitching, and scan compression.

• Handle ATPG pattern generation, simulations, pattern retargeting, and pattern porting.

• Implement and debug MBIST/LBIST solutions.

• Perform DFT timing simulations using SDF and SDC constraints.

• Conduct DRC checks, fault coverage analysis, diagnosis, and debugging.

• Support post-silicon validation, silicon bring-up, and failure analysis.

• Work with JTAG, boundary scan, iJTAG, and SSN technologies.

• Collaborate with RTL, synthesis, STA, verification, and physical design teams.

• Develop automation scripts using TCL, PERL, or Python.

• Provide technical leadership and mentor junior engineers.

Required Skills

• 10+ years of hands-on ASIC DFT experience.

• Strong expertise in SCAN, ATPG, MBIST, and LBIST.

• Experience with Synopsys DFTMAX, TetraMAX, and Siemens Tessent.

• Strong knowledge of scan insertion, scan compression, and scan chain stitching.

• Experience with ATPG simulations, pattern retargeting, and pattern porting.

• Hands-on experience with DFT timing simulations, SDF, SDC, and DRCs.

• Strong debugging, fault diagnosis, and test coverage analysis skills.

• Experience in post-silicon debug and silicon validation.

• Knowledge of RTL, synthesis, LEC, STA, and physical design.

• Experience with JTAG, boundary scan, and iJTAG.

• Strong communication and problem-solving skills.

Preferred Skills

• Siemens Tessent SSN and SMS.

• MBIST post-silicon validation.

• Hierarchical DFT and IP-level integration.

• PSV and design-for-debug methodologies.

• TCL, PERL, or Python scripting.

• Experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.

• Manufacturing test optimization and yield analysis.

Interested candidates can apply through Dice or share their updated resumes with