DRC/LVS Engineer (PDK Development)

Job Summary

We are seeking an experienced DRC/LVS Engineer to support PDK (Process Design Kit) development by building and maintaining high-quality verification decks. The ideal candidate will have strong expertise in translating design rules, ground rules, and design manual specifications into robust verification code.

This role requires a self-driven professional capable of working across multiple technologies and process nodes while ensuring high standards of accuracy and performance.

Key Responsibilities

• Develop and optimize DRC (Design Rule Check) decks based on design and ground rules
• Create and maintain LVS (Layout vs. Schematic) decks for connectivity and verification accuracy
• Translate design manuals and process specifications into verification code
• Support multiple technology nodes and PDK variants simultaneously
• Implement hierarchical and multi-layer rule structures
• Perform testing, validation, and sign-off of verification decks
• Ensure high-quality, maintainable, and scalable verification code

Required Skills & Experience

• 5+ years of experience in DRC and/or LVS deck development
• Strong expertise in rule deck development and validation
• Proficiency in:
  • PxL (Synopsys) – preferred
  • SVRF (Calibre)
• Experience with EDA tools and verification workflows
• Knowledge of hierarchical rule structures and multi-layer verification
• Strong scripting and automation experience

Primary Tools & Technologies

• Synopsys ICValidator (Primary tool)
• Cadence Virtuoso
• Optional: KLayout

Programming & Scripting Languages

• PxL (Synopsys) – required/preferred
• Python – for scripting and automation
• Optional: SVRF (Calibre)

Preferred Qualifications

• Experience with SKILL (Cadence)
• Hands-on experience with Mentor/Siemens Calibre
• Familiarity with LVS methodologies
• Experience with advanced nodes (FinFET, nanosheet, or below)
• Exposure to PDK delivery and sign-off processes
• Proven track record of delivering high-quality verification decks

What You’ll Deliver

• High-quality DRC decks aligned with design rules
• LVS decks for device and connectivity verification
• Clean, maintainable verification code (PxL/SVRF)
• Documentation and validation reports
• Support across multiple technologies and PDK versions

About the Role

This is a critical opportunity to contribute directly to semiconductor PDK development and support next-generation chip design infrastructure. The role demands precision, ownership, and the ability to deliver high-quality verification solutions that engineers rely on for successful tapeouts.