DFT Engineer

Santa Clara, CA, US • Posted 4 days ago • Updated 4 days ago
Full Time
No Travel Required
On-site
$80,000 - $140,000/yr
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Job Details

Skills

  • DFT
  • MBIST
  • RTL
  • ATPG
  • Embedded Systems
  • Debugging
  • EDA
  • Data Analysis
  • Electrical Engineering
  • Communication
  • Semiconductors
  • Test Methods
  • Regulatory Compliance

Summary

Job Title: DFT Engineer
Location: Santa Clara, CA (Onsite)
Job Type: Fulltime

Job Summary

We are seeking an experienced DFT Engineer with strong expertise in Design for Testability (DFT) and Automatic Test Pattern Generation (ATPG) for SoC and ASIC designs. The ideal candidate will be responsible for implementing and validating DFT architectures, generating ATPG patterns, supporting MBIST implementation, and ensuring high test coverage for complex semiconductor products.

Key Responsibilities

< data-start="571" data-end="597">Design for Test (DFT)
  • Develop and implement DFT architectures for complex SoC and ASIC designs.
  • Perform scan insertion and optimize test structures to improve controllability and observability.
  • Validate DFT implementation and ensure compliance with design requirements.
  • Collaborate with design, verification, and physical design teams throughout the development cycle.
< data-start="1246" data-end="1273">MBIST & Memory Testing
  • Implement and validate MBIST architectures for embedded memories.
  • Support memory diagnostics, repair strategies, and test optimization.
  • Analyze memory test coverage and debug memory-related failures.
< data-start="1481" data-end="1500">IO & Clock DFT
  • Develop and validate IO test methodologies for interface and pin-level testing.
  • Implement and verify clock DFT strategies.
  • Ensure proper clock controllability and observability for test modes.
  • Support clock verification and test infrastructure validation.

Required Skills & Qualifications

  • 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
  • Strong understanding of DFT fundamentals including:
    • Controllability
    • Observability
    • Scan-based testing
  • Proven expertise in ATPG pattern generation, analysis, and debug.
  • Experience with MBIST implementation, memory test architectures, and diagnostics.
  • Knowledge of IO test methodologies and pin-level validation.
  • Strong understanding of clock DFT and clock verification concepts.
  • Solid foundation in digital design and RTL fundamentals.
  • Hands-on experience with industry-standard DFT and ATPG EDA tools.
  • Strong analytical, problem-solving, and communication skills.
  • Ability to work effectively in fast-paced semiconductor development environments.

Education

  • Bachelor''s Degree (BE/B.Tech) in Electronics, Electrical Engineering, Computer Engineering, or a related field.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91143212
  • Position Id: 8992681
  • Posted 4 days ago

Company Info

About Signitives

At Signitives, we offer various engagement models to help our clients reach their business goals and get the most value from our product engineering services.

Our engagement models are tailored to fit our clients' unique needs and are designed to be flexible and adaptable.

Our operational methodologies are built on industry-proven frameworks and best practices, and are designed to help us plan, execute, and monitor our projects in a way that maximizes efficiency and minimizes risk.

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AC

Anand Chintakrinda

Recruiter @ Signitives
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