Design For Test (DFT) Engineer

The team is looking for a Design-for-Test (DFT) contractor to test and validate next-generation semiconductor chips. The candidate will be responsible for working with Front End and Physical Design teams to implement DFT and test designs that impact product lines for radio frequency (RF) and Bluetooth/Wireless LAN chipsets.

Job Responsibilities

• Experience with memory BIST Siemens Tessent Flow

• Experience with gate-level simulation and simulation debug

• Experience with automation and scripting Tcl / Perl / Python

• Experience with scan compression SEQ / Ultra / TestKompress

• Experience with ATPG Tetramax

• Experience with ATPG diagnosis, ATE debug, and silicon bring-up

• DFT pattern translation VTRAN

• Experience with RTL design Verilog / SystemVerilog

• Some experience with STA and timing analysis concepts PrimeTime (CDC, clock gating checks, timing constraints)

Required Skills and Experience

• 5+ years of relevant industrial DFT experience

• Excellent problem-solving and debugging skills

• Ability to complete assignments independently