West Coast Consulting LLC
West Coast Consulting LLC

Top Level Integration Engineer

San Jose, CA, US • Posted 13 hours ago • Updated 13 hours ago
Contract W2
On-site
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Semiconductors
  • Physical Data Model
  • Management
  • Layout
  • Routing
  • LVS
  • Debugging
  • Data Analysis
  • EDA
  • Cadence
  • Siemens
  • calibre
  • Synopsys
  • IC
  • Internal Communications
  • Integrated Circuit
  • Assembly
  • Supervision

Summary

Job Description

Title: Top Level Integration Engineer
Location: Onsite 5 days in San Jose, CA

Looking for: Senior semiconductor physical design engineer responsible for integrating individual chip blocks into a complete chip layout, managing bump/RDL routing, resolving DRC/LVS violations, and driving full-chip physical verification through tapeout.

Must-Have Skills
- Full-Chip Physical Integration: Hands-on experience combining multiple GDS/OASIS blocks into a complete chip layout.
- GDS/OASIS: Hierarchical layout assembly, integration, and connectivity verification.
- Bump/RDL Routing: Bump placement, assignment, redistribution layer routing, and chip-package interface.
- DRC/LVS Signoff: Full-chip physical verification, debugging, and violation closure.
- EDA Tools: Cadence Innovus, Siemens Calibre, Synopsys IC Validator, or equivalent.
- Tapeout Experience: Foundry design rules, final GDS/OASIS deliverables, and signoff.
- Independent Ownership: Ability to own full-chip integration from assembly through tapeout without extensive supervision.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: wesca004
  • Position Id: JOB-7416
  • Posted 13 hours ago
Contact the job poster
Rafael Barraza

Rafael Barraza

West Coast Consulting LLC Recruiter @ West Coast Consulting LLC

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