FPGA ENGINEER

FPGA Design Verification EngineerIntroduction:The FPGA Design Verification Engineer will play a crucial role in the team, leading FPGA design verification activities for advanced wireless communication systems. They will be responsible for developing, implementing, and validating DSP algorithms and functional blocks, contributing to phased array and beamforming projects, and ensuring high performance and reliability in FPGA-based systems. Responsibilities:Extensive experience in FPGA design and

Immediate need for a talented High speed Board Design Engineer .This is a 06-12+ months contract opportunity with long-term potential and is location in San Jose, CA/ Sunnyvale, CA(Onsite). Please review the job description below and contact me ASAP if you are interested. Job Diva ID: 26-12621 Pay Range: $ 45 - $50/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location). Key Responsibili

Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early softwarebring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues

Senior Emulation Engineer Exp: 10+ years Location: San Jose, CA Rate: Case to case basis Key Skills: Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-u