Physical Design Engineer

Title :: Physical Design Engineer

Location :: Sunnyvale, CA (Onsite)

We are seeking a Physical Design Engineer with extensive industry experience to join our world-class silicon engineering team in Sunnyvale, California. This role is designed for highly accomplished engineers who have successfully delivered multiple complex SoCs from architecture through tapeout in advanced technology nodes (7nm, 5nm, 3nm, and below). You will work closely with Architecture, RTL, DFT, Logic Design, Packaging, and Foundry teams to develop next-generation semiconductor products that power cutting-edge AI, HPC, networking, mobile, and data center applications.

Key Responsibilities

• Lead end-to-end physical design implementation for complex SoC, subsystem, and IP blocks.
• Drive floorplanning, power planning, placement, clock tree synthesis (CTS), routing, timing closure, and physical verification activities.
• Own challenging timing, congestion, power, and signal integrity closure issues at advanced process nodes.
• Develop and optimize methodologies for physical design automation, reproducibility, and scalability.
• Collaborate with cross-functional teams to refine architecture and RTL for optimal PPA (Performance, Power, and Area).
• Analyze and resolve setup/hold violations, IR drop, electromigration (EM), crosstalk, and thermal issues.
• Lead design reviews and provide technical direction to junior and senior engineers.
• Work closely with foundries and EDA vendors to enable advanced process technologies.
• Drive tapeout readiness and ensure successful first-pass silicon execution.
• Establish best practices and contribute to long-term physical design strategy.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• Master's degree or PhD strongly preferred.
• 6-10 years of industry experience in VLSI Physical Design.
• Proven track record of delivering multiple successful SoC tapeouts in advanced technology nodes (7nm, 5nm, 3nm, or beyond).
• Deep expertise in:
  • Floorplanning
  • Power planning
  • Placement optimization
  • Clock Tree Synthesis (CTS)
  • Physical synthesis
  • Timing closure
  • Routing and signoff
  • ECO implementation
• Strong understanding of:
  • STA (Static Timing Analysis)
  • MCMM timing closure
  • Signal Integrity
  • IR Drop Analysis
  • Electromigration
  • Low-Power Design Techniques
• Expertise with industry-standard EDA tools such as:
  • Cadence Innovus
  • Synopsys ICC2
  • PrimeTime
  • Tempus
  • StarRC
  • RedHawk
  • Calibre
• Strong scripting skills in Tcl, Python, Perl, or Shell.
• Excellent debugging, analytical, and problem-solving skills.