PCB Layout Engineer

Job Summary

Meta is seeking an experienced PCB Layout Engineer with advanced expertise in Cadence Allegro PCB and complex, high-density PCB layout. The ideal candidate will have strong experience designing high-speed server and hardware boards involving advanced memory interfaces, PCIe, high-speed digital, analog, mixed-signal, and power domains.

Cadence Allegro Layout 23.1 or higher is mandatory.

Key Responsibilities

• Own end-to-end PCB layout for complex, high-density designs used in data center server boards.
• Perform high-speed digital PCB layout for:
  • HBM
  • DDR4/DDR5
  • PCIe Gen 5/Gen 6
  • USB 3.2 or higher
• Implement controlled impedance, length matching, and crosstalk mitigation.
• Develop and enforce PCB layout design rules across high-speed digital, analog, mixed-signal, and power domains.
• Collaborate with electrical engineers to review schematics and provide layout-driven feedback.
• Provide recommendations regarding component placement, power distribution, and signal routing.
• Partner with mechanical engineers to resolve board outline, connector placement, thermal, and stack-up constraints.
• Drive DFM reviews with contract manufacturers and PCB fabricators.
• Ensure PCB layouts meet quality, yield, and reliability requirements.
• Maintain and improve PCB design standards, layer stack-up libraries, and footprint libraries.
• Support prototype and production boards with layout documentation, net tracing, and design revision analysis.

Required Skills & Qualifications

PCB CAD / Layout

• Advanced proficiency in Cadence Allegro PCB for PCB layout and design.
• Cadence Allegro Layout 23.1 or higher – Mandatory.
• 10–14 years of CAD experience.
• Strong knowledge of CAD software for 2D and 3D design applications.
• Hands-on experience with HDI microvia technology, including blind and buried vias.

High-Speed PCB Design

• Experience designing complex SoC, microprocessor, or FPGA-based PCBs.
• Experience with high-density, high-speed memory designs such as:
  • DDR5
  • LPDDR5
  • HBM
• Experience with PCIe Gen 5 / Gen 6.
• Experience with power delivery and mixed analog/digital PCB designs.
• Strong knowledge of high-speed signal integrity and constraint-driven design.

Constraints & Manufacturing

• Deep knowledge of Cadence Constraint Editor (CES).
• Experience with high-speed constraint-driven PCB designs.
• Strong understanding of:
  • DFA – Design for Assembly
  • DFM – Design for Manufacturing
  • DFT – Design for Test
• Experience ensuring PCB fabrication and assembly quality.

Preferred Experience

• Intel-based or similarly complex SoC/microprocessor/FPGA PCB design experience.
• Data center server board design experience.
• Experience working with contract manufacturers and PCB fabricators.
• Experience with complex multilayer and HDI PCB technologies.
• Experience supporting prototype-to-production hardware development.