Validation Engineer

Cupertino, CA, US • Posted 9 hours ago • Updated 9 hours ago
Contract Corp To Corp
Contract W2
12 Months
Able to Sponsor
On-site
$60 - $65/hr
Fitment

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Job Details

Skills

  • Post-Silicon Validation
  • Silicon Bring-up
  • RTL Simulation (SystemVerilog/UVM/VCS/Questa/Xcelium)
  • EDA Emulation (Palladium/Zebu/Veloce)
  • Python/C/C++ Programming
  • Hardware Debug & Failure Analysis
  • Computer Architecture & Chip/System Validation
  • Machine Learning Hardware/AI Accelerator Validation

Summary

Job title : Validation Engineer
Location: Cupertino, CA and Austin TX
Experience: 5+ Years
Seekiing- Post-Validation Engineer with experince in knowledge of the full validation lifecycle from RTL simulation (SystemVerilog/UVM, VCS, Questa, Xcelium) and emulation (Palladium, Zebu, Veloce) through silicon failure analysis and debug.
What You'll Be Doing:
As a Senior Validation Engineer on our Machine Learning Acceleration team to work from early design validation through emulation, silicon bring-up, post-silicon validation, and ongoing support of production systems deployed in AWS data centers. You'll collaborate deeply with architecture, RTL design, design verification, firmware, and software teams to ensure our next-generation AI/ML accelerators meet the highest standards of quality and performance. This role requires bridging multiple domains and broad scope of impact from low-level hardware interfaces to high-level ML workloads to deliver exceptional results.
A day in the life:
What We Are Looking For:
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10511336
  • Position Id: 9048177
  • Posted 9 hours ago
Contact the job poster
Andrew Fugle

Andrew Fugle

Della Infotech Recruiter @ Della Infotech
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