Physical Design Engineer


dBestWorkz LLC
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Job Details
Skills
- TSMC
- 2NP
- 3NP
- DRC
- LVS
- ERC
Summary
Location : Palo Alto, CA (Full Onsite)
· Exposure to TSMC 2NP/3NP is must
· Perform endtoend physical design flow:
o Floorplanning
o Power planning (PG grid, IR)
o Placement & optimization
o CTS (Clock Tree Synthesis)
o Routing
o Postroute optimization
· Achieve timing closure across all modes and corners
· Resolve DRC, LVS, ERC and signoff violations
· Handle lowpower design techniques:
o MultiVt, Multivoltage (UPF)
o Power gating, clock gating
· Perform physical verification and signoff:
o STA (Primetime)
o SI / Crosstalk
o IR drop & EM analysis
· Work on advanced nodes (7nm, 5nm, 3nm or below)
· Collaborate with:
o RTL & Microarchitecture teams
o DFT & Test engineers
o Foundry and CAD teams
· Debug complex timing, congestion, power, and variability issues
· Drive methodology improvements and automation (scripts/flows)
- Dice Id: 91142964
- Position Id: 9109261
- Posted 5 hours ago
Company Info
About dBestWorkz LLC
DBestWorkz LLC is a strategy-led technology services company delivering AI-driven and end-to-end IT solutions for organizations looking to scale with confidence.
We partner with businesses from strategy to execution—helping define technology roadmaps, design secure architectures, and build production-ready systems that drive measurable business outcomes.
Our expertise spans:
AI, GenAI & Data Engineering (RAG, agentic systems, analytics platforms)
Enterprise IT Solutions (cloud, DevOps, integrations, SAP/Oracle ecosystems)
Digital Transformation & Modernization
Scalable, secure, and compliant system design
We combine deep technical expertise, experienced delivery teams, and a results-first mindset to reduce friction, accelerate time-to-value, and ensure solutions work in the real world—not just on paper.
What sets us apart:
✔ Strategy-led execution
✔ Production-ready AI and IT systems
✔ Enterprise-grade security and scalability
✔ Clear ownership and outcome accountability

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