Staff Physical Design Engineer

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

Physical Design Engineer ContractIntroduction: We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering teams. Responsibilities: Execute RTL synthesis for complex ASIC and SoC d

Required Qualifications: Bachelor s/Master s degree in Electrical Engineering or related field5 10 years of experience in RTL design and microarchitectureStrong expertise in RTL design using SystemVerilog/VerilogMicroarchitecture development for complex digital systemsPerformance optimization and pipelining techniquesExperience with simulation and debugging tools such as:Synopsys VCS / Cadence XceliumFamiliarity with synthesis and timing concepts (e.g., using Synopsys Design Compiler)Strong unde

Sr. Staff Engineer, ASIC Design Location: San Jose (on-site) Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world's leading semiconductor ecosystem, Ayar Labs' co-packaged o