RFIC Layout Engineer

San Francisco, CA, US • Posted 1 day ago • Updated 1 day ago
Full Time
On-site
Fitment

Dice Job Match Score™

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Job Details

Skills

  • Energy
  • Mixed-signal Integrated Circuit
  • Crystal Reports
  • User Experience
  • VLSI
  • RTL
  • Emulation
  • Research
  • Wireless Communication
  • RFIC
  • Intellectual Property
  • IP
  • System On A Chip
  • Art
  • Radio
  • CMOS
  • calibre
  • LVS
  • Cadence
  • Layout
  • RF
  • Routing
  • Communication
  • Perl

Summary

The Wireless SoC Radio Team designs state-of-art highly energy efficient CMOS radios, from RF to bits. To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and mixed-signal blocks from RF front-end amplifiers to data converters, including baseband filters, baseband and RF phase-locked loops, crystal oscillators, and bandgap references.\\n\\n We are working on new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.

As an RFIC Layout Designer, you will be a key member of a RFIC team, researching, designing and bringing the next-generation of wireless technologies into high-volume production in advanced CMOS technology nodes. In this role, you will work closely with the RFIC design team to layout and verify custom RF and analog IP for complex SoC products. You will have a critical impact on developing Apple's state-of-the-art radios and getting them into hundreds of millions of products.

5+ year minimum related experience required.\nExperience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS.\nHigh level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology.\nKnowledge of Cadence layout tools.

Knowledgeable in layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing.\nSolid understanding of RC delay, electromigration, and coupling.\nUnderstanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE.\nExcellent communication skills and able to work with cross-functional teams.\nScripting skills in PERL or SKILL.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90733111
  • Position Id: e5edf29ed4077114587af5e7d7ba201f
  • Posted 1 day ago
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