Mountain View, California
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Today
Position:Design Verification Engineer Job Description:What You'll Be Doing:Candidate roles and responsibilities: Responsible for analyzing and capturing requirements, Functional Testplan development, Verification plan development related to Consumer Electronics and AI ASICs, Mixed Signal ASICsResponsible to create reusable verification environment in System Verilog, UVM (Universal Verification Methodology) based on the strategy using Ethernet UVM VIPs and models. Verification environment includ
Full-time



