DFT Verification Engineer

Job Title: DFx Verification Engineer (DFT Verification) - Semicon company

Location: Santa Clara, CA (Onsite)
Duration: Contract
Open Positions: 15
Experience: 4+ Years

Role Overview

We are looking for skilled DFx Verification Engineers with strong experience in Design-for-Test (DFT) verification. The ideal candidate will be responsible for validating DFx features including scan, BIST, JTAG, and low-power test scenarios using SystemVerilog/UVM-based environments.

Key Responsibilities

• Develop and execute verification plans for DFx features, including:
  • Scan (stuck-at, transition fault)
  • MBIST / LBIST
  • Boundary Scan (JTAG)
  • Memory repair and redundancy
  • Low-power test scenarios
• Build and maintain testbenches using SystemVerilog/UVM
• Perform verification of:
  • Scan chain integrity and connectivity
  • Test mode functionality and coverage
  • ATPG pattern validation and debugging
  • BIST controllers and memory test logic
• Collaborate with design and DFT teams to ensure robust test coverage
• Debug and analyze failures using waveform and debug tools

Required Skills

• Strong understanding of DFT concepts:
  • Scan, ATPG, MBIST, JTAG
• Solid foundation in digital design fundamentals
• Hands-on expertise in:
  • SystemVerilog and UVM
  • Simulation tools such as VCS, Xcelium, or Questa
• Experience with ATPG tools:
  • TetraMAX, Modus, or FastScan
• Proficiency in debug tools like Verdi or DVE
• Understanding of:
  • Low-power design (UPF/CPF)
  • Clocking and reset strategies

Preferred Qualifications

• Experience with large-scale SoC verification
• Familiarity with low-power DFx validation
• Strong debugging and problem-solving skills
• Ability to work in a fast-paced, collaborative environment