Design Verification Engineer- PCIe

San Jose, CA, US • Posted 3 hours ago • Updated 3 hours ago

Full Time

No Travel Required

On-site

Depends on Experience

Fitment

Dice Job Match Score™

👾 Reticulating splines...

Job Details

Skills

Design Verification
UVM
System Verilog
Verilog
PCIe
PCIe Architecture
Micro-Architecture
Full-chip Test
Debug
SoC
Silicon
Gen 4/5
PCIe6
UCIe
C
C++

Summary

Description:

The Design Verification (DV) engineer at Client’s is involved in the functional verification of PCIe controller and PCIe-phy at block, sub-system and MLSoC level. Will also be involved in PCIe bring-up and debug on emulator. Generate required PCIe controller and phy initialization (register programming code sequence) for PCIe

Required Background:

BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 12+ years of experience in functional verification and silicon bring-up/debug.
Very good current working experience of UVM and System Verilog based verification methodology is a must.
Working experience on PCIe protocols Gen4/5.
Working experience on PCIe bring-up and debug on Silicon is a plus.
Past working experience on UCIe protocols is a plus.
Proficiency in C/C++/Python programming is a plus.
Good debug and problem solving skill.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 90979286
Position Id: 8930437
Posted 3 hours ago

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