FPGA Verification Engineer - Mountain View, CA- HYBRID

Onsite Position Preferred Experience: Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or similar tools Exposure to RTL design, software development, formal verification, or other related domains Good understanding of computer organization / architecture Experience or familiarity with formal tools and/or functional verification tools from VCS, Cadence, Mentor Graphics Key Responsibilities: Write tests, sequences, and testbe

Role:PCIe Verification Engineer Rate:Market rate - Submit at the best rate. Position Type: Contract Location:San Jose, CA Or Silver Lake, CO. Job Description: Experience:7+ YearsEducation:Bachelor/Master of Engineering (B.E./B.Tech/MS) in Electronics, Electrical, Computer Engineering, or a related field Role Summary: Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4, Gen5, and Gen6 specifications. Utilizing SystemVerilog and UVM, yo

Role: Principal Engineer, Design Verification (NPU) Location: Mountain View, CA (Onsite) Job Type: Contract Project description The Principal Design Verification Engineer, within the NPU Hardware & Software organization, is intended for an individual with a broad background in design verification and complex digital system validation, with significant experience in AI accelerator verification and automotive safety standards. This role is responsible for driving the verification excelle

General Skills: Expert communicator across global, cross-cultural, and cross-functional teams. Strong analytical, system level, and architectural thinking. Proven ability to lead technical initiatives without direct authority. High bar for design correctness, validation, and quality. Collaborative mindset across hardware, software, and verification organizations. Required Specialized Skills: Extensive experience in RTL design using Verilog/SystemVerilog for complex digital systems, preferably NP