Digital Design Implementation Engineer
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Position: Digital Design Implementation Engineer (San Jose, CA)
Job Overview:
The company is seeking a talented and highly motivated Digital Design Implementation Engineer to join its SoC R&D team in San Jose, California. This individual will play an integral role in the development of digital designs for wireless communication systems and high-speed PHY applications, supporting the implementation process from RTL through signoff-quality silicon.
The ideal candidate will have hands-on experience with ASIC design implementation, including logic synthesis, static timing analysis, and/or place and route. This role offers the opportunity to collaborate with cross-functional engineering teams, develop and optimize implementation methodologies, and drive improvements in power, performance, and area (PPA) to support advanced semiconductor development.
This is a contract role.
Key Responsibilities:
- Perform ASIC design implementation across one or more areas, including logic synthesis, static timing analysis (STA), and place and route (PnR).
- Develop, maintain, and optimize design implementation flows, methodologies, and automation scripts.
- Drive timing, power, and area (PPA) optimization and closure to achieve design performance and implementation objectives.
- Execute timing signoff activities, including developing and validating Synopsys Design Constraints (SDC), analyzing timing reports, and resolving timing violations.
- Collaborate closely with RTL design, Design for Test (DFT), and physical design engineering teams to identify and resolve implementation challenges.
- Support silicon bring-up, validation, and commercialization activities.
- Contribute to continuous improvements in design quality, implementation efficiency, and engineering workflows.
Qualifications:
<>Required
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline.
- Minimum of 2 years of hands-on ASIC design implementation experience in at least one of the following areas: static timing analysis (STA), logic synthesis, or place and route (PnR).
- Experience with industry-standard electronic design automation (EDA) tools, such as:
- Synopsys Design Compiler, Fusion Compiler, or PrimeTime.
- Cadence Genus, Innovus, or Tempus.
- Strong understanding of digital design fundamentals, timing analysis concepts, and design constraints.
- Proficiency in scripting languages such as Tcl, Python, Perl, or shell scripting.
- Strong analytical, problem-solving, and troubleshooting skills.
- Excellent written and verbal communication skills, with the ability to collaborate effectively across multidisciplinary engineering teams.
- Demonstrated teamwork, initiative, dedication, and strong interpersonal skills.
<>Preferred
- Experience implementing high-speed digital designs, including SerDes, high-speed PHY, or high-frequency digital blocks.
- Experience working with advanced semiconductor process nodes.
- Familiarity with clock tree synthesis (CTS) and multi-corner, multi-mode (MCMM) timing analysis and closure.
- Knowledge of low-power design methodologies, including Unified Power Format (UPF).
- Familiarity with physical verification and signoff methodologies, including IR drop and electromigration (EM) analysis.
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Saige Partners, one of the fastest growing technology and talent companies in the Midwest, believes in people with a passion to help them succeed. We are in the business of helping professionals Build Careers, Not Jobs. Saige Partners believes employees are the most valuable asset to building a thriving and successful company culture, which is why we offer a benefit package and convenient weekly payment solutions that helps our employees stay healthy and maintain a positive work/life balance. Contact us to learn more about the opportunity below or check out other opportunities at .
