Company:Qualcomm Technologies, Inc.
Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:We are seeking a highly skilled and experienced engineer to develop system-technology co-optimized solutions for the slowing Moore's law era. The focus is on identifying and driving individual process technology components to achieve the best E2E system KPIs of AI and other emerging workloads scalable across different BUs. Multiple and varied individual technology components and their interactions across the system stack drive the E2E system KPIs.
The E2E system KPIs for AI and emerging workloads include the power, performance and TCO of the entire system. The underlying technology components driving the E2E KPIs are as varied as tech node compute IPs, SRAM, DRAM, NVM multi-hierarchical memories, electrical and optical networking, 2.5D/ 3D/3.5D chiplets. The primary role of the candidate is to comprehend these individual components and the way they interact to deliver the best system solution. The candidate also needs to make sure that the solutions are scalable across different business units (BUs) from datacenters to physical AI to computing devices.
To drive these technologies the person will collaborate with high-level representatives across functional teams (e.g. Architecture, product management, Design teams) and external (Foundry, Memory vendors) to develop and execute an implementation strategy that meets system requirements.
Key Skills- Thorough understanding of E2E system KPI dependency e.g. power, performance and TCO on the underlying process technology components and the ability to identify and drive the key individual process components and architectures.
- Good knowledge of underlying components e.g. tech node, logic IPs, SRAM, DRAM, NVM memory architecture, electrical and optical networking and 2.5D, 3D, 3.5D integration schemes and their interactions and trade-offs for E2E KPI optimization.
- Ability to model and script (with internal/ external tools) the system use case impact of 3D, 3.5D integration of process tech node logic, 3D SRAM and DRAM architectures and networking (electrical and optical).
- Ability to map emerging system use cases to hardware, chiplet and process architecture solutions; and vice versa
Other Skills:- Exceptional creativity to innovate new ideas and develop innovative products/ processes without established objectives or known parameters.
- Verbal and written communication skills to convey highly complex and/or detailed information. Will require strong negotiation and influence with large groups or high-level constituents
- Ability to work independently and as part of a team
- Most tasks do not have defined steps; simultaneous use of multiple mental abilities is generally required to determine the best approach
- Deductive and inductive problem solving is required; multiple approaches may be taken/necessary to solve the problem; often information is missing or conflicting; advanced data analysis and interpretation skills are required.
Minimum Qualifications: Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Preferred Qualifications:- Master's or Ph.D. in Electrical Engineering, Computer Science, or a related field
- 12+ years of ASIC design, verification, validation, integration, or related work experience.
- 4+ years of experience with architecture and design tools.
- 4+ years of experience with scripting tools and programming languages.
- 4+ years of experience with design verification methods.
- 2+ years of work experience in a role requiring interaction with senior leadership (e.g., Vice President level and above).
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Pay range and Other Compensation & Benefits: $192,000.00 - $288,000.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
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