Verification Consultant

Austin, TX, US • Posted 10 days ago • Updated 10 days ago
Contract Independent
6 Months
No Travel Required
On-site
$75 - $93/hr
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Job Details

Skills

  • AXI
  • UVM
  • SystemVerilog
  • System On A Chip
  • CHI

Summary

6 months

Start Date – August 31

Austin, TX (onsite) – San Jose can be an option for perfect candidate

Pay Rate - $93/hr

Must Be W-2

Must Have:

Gate Level Simulation Ownership is most important….needs to have this experience.

UVM/System Verilog Experience

High performance computing background would be a huge +…someone from AMD, Qualcomm, etc

AXI/CHI protocols

 

Position Details

Vertical Description

Technical
As a Senior Staff System IP Design Verification Contractor you will contribute to the functional verification of System IP including coherent interconnect and caches. This is a technical individual contributor role with heavily involved hands-on project execution. A strong background in Design Verification and hands-on experience with both block-level and top-level is required to be successful in this role.

Key responsibilities include:
• Owning Gate-level simulations TB bringup
• Owning power-aware verification with UPF
• Collaborating with Physical design teams, running and debugging gate-level simulations
• Working with SoC team to debug functional fails during IP bringup and feature execution
• Creating test benches, verification environments, stimulus, tests
• Collaborating with designers to verify the correctness of a design feature, and resolve fails
• Developing assertions, checkers, covergroups, Systemverilog constraints
• Debugging and root causing functional fails from regressions
• Analyzing code and functional coverage results, performing gap analysis
• Helping with Silicon bringup and root causing fails

Requirements

• PhD/MS/BS in Electrical or Computer Engineering • 12+ years industry experience in a design verification role • Expert hands-on coding skills in Testbench, Stimulus, checkers development, coverage closure. • Experience with System Verilog, UVM or equivalent • Atleast 5+yrs of experience with Gate-Level simulations • Knowledge of ARM protocols or equivalent protocols – CHI, AXI, ACElite, APB • Experience with Git version control, Unix/Perl/Python scripting • Good written and verbal communication skills

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10308440
  • Position Id: #587673
  • Posted 10 days ago

Company Info

About Technical Link

Technical-Link North America is dedicated to excellence in engineering staffing, connecting top talent with leading companies. Whether you're an employer seeking skilled engineers or an engineer looking for your next contract opportunity, we have the expertise and resources to meet your needs.

Contact the job poster
LS

Lekenzey Siddell

Recruiter @ Technical Link
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