Analog Designer at San Jose, CA

Job Title: Analog Designer Job ID:26-02483 Location: CA, SAN JOSE Duration: 12 months on W2 contract Description: JOB DUTIES: Design and verify standard cell schematics. Port schematics into new technologies. Create new schematics for new functionality requirements. Verify circuit robustness using Monte Carlo simulation. Characterize standard cell libraries for custom PVTS. EXPERIENCE AND EDUATION: 10+ years of relevant work experienceExperience with Schematic DesignExperience with Circuit Sti

Job Description JOB DUTIES: Design and verify standard cell schematics. Port schematics into new technologies. Create new schematics for new functionality requirements. Verify circuit robustness using Monte Carlo simulation. Characterize standard cell libraries for custom PVTS. EXPERIENCE AND EDUATION: 10+ years of relevant work experience;Experience with Schematic Design;Experience with Circuit Stimulation using Spice;Experience in Standard Cell Characterization using industry standard tools.

Duration: 12+ months contract Location: San Jose, CA (Onsite, 5 days/week) Description: PCB Development: Lead the schematic entry, component selection, and layout routing optimization for complex RF evaluation boards using Cadence Allegro.Simulation & Analysis: Perform Signal Integrity (SI) and Power Integrity (PI) simulations. Utilize Ansys HFSS for EM modeling and impedance matching to ensure optimal RF performance.Hardware Bring-up: Own the board bring-up process, including debugging hardware

Position - Signal Integrity Engineer Location - San Jose, USClient: Direct Client We have an urgent opening for a Signal Integrity Engineer to work on next-gen Security and Enterprise Routing systems. Key ResponsibilitiesDesign & analyze high-speed digital/analog systemsPerform signal integrity (SI) simulations and PCB (pre/post-layout) analysisWork on power delivery networks (PDN) / power integritySupport prototype bring-up, validation & troubleshootingCollaborate with hardware, layout & valida