SoC Design Verification Engineer

Position: DV SOC / SoC Design Verification Engineer Location: Remote Job Type: Contract Job SummaryWe are looking for an experienced SoC Design Verification Engineer to support SoC-level verification, integration, and signoff activities for complex ASIC/SoC designs. The ideal candidate will have strong hands-on experience with SystemVerilog, UVM, SoC verification, RAL, low-power verification using UPF, Gate-Level Simulation (GLS), and coverage closure. This role will involve integrating IPs/UVCs

Position: DV IP Design Verification Engineer Location: Remote Employment Type: Contract Job SummaryWe are looking for an experienced Design Verification Engineer with strong expertise in IP/Block-level verification to support verification of complex digital IPs. The ideal candidate will have hands-on experience developing SystemVerilog/UVM-based verification environments, creating verification plans and testcases, debugging RTL and testbench issues, and driving functional/code coverage to closur

Must Requirement : End-to-end UVM experience from scratch (across test bench infra development, debug, scoreboard etc.) Protocol experience like Ethernet, UCIe, PCIe is a plus but it is not mandatory like the end-to-end UVM expertise. Key Responsibilities Block-Level Verification Ownership: Take full technical ownership of verifying 4-5 complex design blocks per project, ensuring high-quality verification sign-off.Testbench & Component Development: Build and maintain verification components, te

We are seeking a highly skilled Physical Design Engineer to drive block-level implementation and optimization activities for advanced ASIC/SoC designs. The ideal candidate will have strong expertise in physical design flow, timing, power, area optimization, and tape-out support. Key Responsibilities: Execute block-level physical design implementation from floorplan to tape-out.Develop and optimize floorplans, macro placement, and power-aware design methodologies.Perform placement optimization to