Physical Design Engineer

Job Title: Physical Design Engineer Location: Mountain View, CA Onsite Openings: 2 Experience: 5 10 Years Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on experience in advanced-node SoC physical design, particularly TSMC 3nm/2nm technologies. The ideal candidate will have experience working on high-performance, low-power SoC/GPU designs and should be capable of owning the physical implementation flow from netlist through GDSII/tapeout. Key Responsib

Physical Design Engineer (PnR / PPA / Timing Closure) Mountain View CA Open to Both FTE and Contract Option Salary: Market We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and

Job Title: Physical Design Engineer Location: Mountain View, CA (Onsite) Experience: 5 -10 years in Physical Design Mandatory Skill: Innovous, 2nm, 3nm, 4nm, 5nm Job Description: Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys Fusion Compiler, In

Employment Eligibility Statement: Due to specific project and client requirements, this position is open to U.S. Citizens and U.S. Lawful Permanent Residents (s). Sponsorship is not available at this time. Danta Technologies evaluates all candidates in compliance with the Immigration and Nationality Act (INA) and EEOC guidelines. All hiring decisions are made without regard to race, color, religion, sex, gender identity, sexual orientation, national origin, age, disability, veteran status, or an