About the role
You will own the power-analysis flows that a large silicon team uses to estimate and
sign off power on its SoCs, from RTL to gate level. You will develop and release
in-house tools built around Synopsys power tools, support the design teams that run
them, carry out power studies on full-chip designs, and work with Synopsys on tool
issues. The team also uses AI agents to launch runs, debug failures and write reports,
and you will maintain and extend them.
Responsibilities
Develop, maintain and release in-house Python and Tcl wrappers around
Synopsys PrimePower, PrimeTime PX, PrimePower RTL and RTL Architect,
covering gate-level power (averaged, time-based, glitch and vectorless) and RTL
power.
Own the release cycle: versioned releases, release notes, user guides and
tutorials, fixes to released versions, and user support in internal Q&A forums.
Keep the nightly regression suites passing on reference designs across process
nodes, and add a test for every fix.
Support design teams' power runs: set up inputs (netlist, SDC, SPEF, UPF,
libraries, activity files), debug failed runs, and judge whether results can be
trusted (annotation coverage, choice of activity window, comparison with earlier
design milestones).
Run power studies on large designs, for example a campaign of more than 100
tests on a full-chip network-on-chip. Derive metrics such as energy per byte,
per-block and per-power-domain attribution, clock-gating efficiency, and glitch
and leakage breakdowns.
Find the root cause of tool, library and flow problems, such as memory power
rails, power-switch definitions and PDK updates. Build small testcases and work
with Synopsys support and R&D.
Produce power data for others: power-tracker spreadsheets, dashboards, and
power maps for thermal and IR-drop tools.
Build and maintain AI-agent automation for the power team: launching and
monitoring runs, analysing failures, checking inputs before expensive runs, and
filing bugs automatically.
Required
8+ years in SoC power analysis or low-power methodology, including 3+ years
building flows that other engineers use.
Hands-on gate-level power analysis with PrimePower or PrimeTime PX:
averaged and time-based modes, FSDB and SAIF annotation, glitch power and
vectorless analysis.
RTL power estimation with PrimePower RTL, RTL Architect or an equivalent tool
(for example Cadence Joules).
Low-power design: UPF, power domains and switches, isolation and retention,
clock gating, multiple voltages, memory power states.
Strong Python, as used in production tools that many engineers depend on
(command-line tools, YAML and template-driven configuration, tests, code
review). Tcl in Synopsys shells, plus csh and bash.
Working knowledge of implementation data: Liberty libraries, netlists, SDC, SPEF
and UPF from synthesis and place-and-route.
Ability to trace a problem from logs and reports to its root cause, and to explain
power results clearly to designers and architects.
Linux, compute farms (LSF or similar), version control and code review.
