Verification Engineer 3

We are looking for Verification Engineer 4 for our client in Markham, ON Job Title: Verification Engineer 4 Job Location: Markham, ON Job Type: Contract Job Overview: Requirement/Must Have: Minimum 5 years of proven verification experience on large ASIC development projects or software/firmware experience in a hardware development setting.Strong background in C/C++ development in a Linux Environment.Strong debug skills and experience with debug tools such as Gdb, Valgrind.Proficient in Object Or

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

Staff Engineer, Digital Verification Company Description Butterfly Network, Inc. (NYSE: BFLY) is driving a digital revolution in ultrasound imaging and sensing with its proprietary Ultrasound-on-Chip semiconductor technology and software solutions. Butterfly first proved its technology in the point-of-care ultrasound market - commercializing the world's first single-probe, whole-body portable ultrasound device, which is now on its best-selling, third-generation: Butterfly iQ3 . The Company com

Position:Senior Design Verification Engineer (eInfochips Inc) Job Description:What You\'ll Be Doing: Testbenches: Build scalable verification environments using UVM and SystemVerilog.Planning: Create detailed verification plans from architectural specifications.Execution: Write, run, and debug constrained-random tests and directed tests.Coverage: Define, measure, and close functional and code coverage metrics.Gate-Level: Run gate-level simulations to verify power-up and timing states.Automation