Layout Design Engineer with SRAM Experience

Santa Clara, CA, US • Posted 1 day ago • Updated 1 day ago
Full Time
No Travel Required
On-site
Depends on Experience
Fitment

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Job Details

Skills

  • Layout
  • SRAM

Summary

Sr. Layout Design Engineer with SRAM Experience

Location : Santa Clara, CA

Location : Remote

 

· 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.

· Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.

· Solid grasp of SRAM and memory layout principles.

· Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.

· Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.

· Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.

 

 

 “Tekshapers is an equal opportunity employer and will consider all applications without regards to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.”

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10335759
  • Position Id: 28576-17456-
  • Posted 1 day ago
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JP

Job Poster

Recruiter @ TekShapers
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